`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   18:16:51 11/30/2012
// Design Name:   MEM_RD_DUAL
// Module Name:   D:/Workspace/xilinx workspace/HFM_DETECTOR/mem_rd_dual_simu.v
// Project Name:  HFM_DETECTOR
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: MEM_RD_DUAL
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module mem_rd_dual_simu;

	// Inputs
	reg clk;
	reg rst;
	reg [15:0] ch1_to_rd_r;
	reg [15:0] ch1_to_rd_i;
	reg [15:0] ch2_to_rd_r;
	reg [15:0] ch2_to_rd_i;
	reg [15:0] addr_wr;

	// Outputs
	wire [15:0] ch1_rd_r;
	wire [15:0] ch1_rd_i;
	wire [15:0] ch2_rd_r;
	wire [15:0] ch2_rd_i;
	wire [8:0] addr_rd_ch1;
	wire [8:0] addr_rd_ch2;

	// Instantiate the Unit Under Test (UUT)
	MEM_RD_DUAL uut (
		.clk(clk), 
		.rst(rst), 
		.ch1_to_rd_r(ch1_to_rd_r), 
		.ch1_to_rd_i(ch1_to_rd_i), 
		.ch2_to_rd_r(ch2_to_rd_r), 
		.ch2_to_rd_i(ch2_to_rd_i), 
		.addr_wr(addr_wr), 
		.ch1_rd_r(ch1_rd_r), 
		.ch1_rd_i(ch1_rd_i), 
		.ch2_rd_r(ch2_rd_r), 
		.ch2_rd_i(ch2_rd_i), 
		.addr_rd_ch1(addr_rd_ch1), 
		.addr_rd_ch2(addr_rd_ch2)
	);
	
	integer i;
	always #10 clk = ~clk;
	
	always #500 addr_wr = addr_wr + 1;
	
	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 0;
		ch1_to_rd_r = 0;
		ch1_to_rd_i = 0;
		ch2_to_rd_r = 0;
		ch2_to_rd_i = 0;
		addr_wr = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		rst = 1;
        
		// Add stimulus here
		for(i=0;i<500;i=i+1)
			#20 
			begin
			ch1_to_rd_r = i;
			ch1_to_rd_i = i;
			ch2_to_rd_r = 2*i;
			ch2_to_rd_i = 2*i;
			end

	end
      
endmodule

